The present invention relates generally to liquid crystal display devices and, more particularly, to a technique adaptable for use with segment drivers in liquid crystal display devices of the simple matrix type.
Simple matrix type liquid crystal display devices such as liquid crystal display modules of super twisted nematic (STN) schemes for example are widely employed as display devices for use in notebook personal computers (PCs) and others.
FIG. 6 is a diagram showing a configuration of equivalent circuitry of a prior known liquid crystal display panel of presently available STN liquid crystal display modules along with peripheral circuitry.
The liquid crystal display panel is designated by numeral 101 and is designed to include a pair of glass substrates spatially opposing each other with a layer of liquid crystal disposed therebetween, wherein one glass substrate has its liquid crystal side surface on a plurality of parallel common electrodes 11 which are formed in such a manner that these extend in a direction xe2x80x9cXxe2x80x9d and laid out in a direction xe2x80x9cYxe2x80x9d with each of the plurality of common electrodes 11 being connected to a corresponding one of common drivers as provided in a common driver unit 103.
The other glass substrate has a liquid crystal side surface on which a plurality of parallel segment electrodes 10 are formed in a manner such that they extend in the direction Y and arrayed in the direction X with each of the plurality of segment electrodes 10 being connected to a corresponding one of segment drivers in a common driver unit 102.
The plurality of segment electrodes and the plurality of common electrodes intersect each other at crossover points, each of which constitutes a picture element or xe2x80x9cpixelxe2x80x9d region, wherein the pixels are driven by applying drive voltages from respective segment drivers of said segment driver unit 102 to said plurality of segment electrodes 10 while applying drive voltages from respective common drivers of said common driver unit 103 to said plurality of common electrodes 11.
Simple-matrix liquid crystal display devices are typically driven with time-division methods, one of which is the so-called line-sequential driving method that includes the steps of sequentially selecting one by one the common electrodes (or scan electrodes) within a single scanning time period and then applying a drive voltage to each pixel of the liquid crystal within this select period.
The line-sequential drive methodology typically includes an xe2x80x9cAlt Pleshkoxe2x80x9d drive method (also known as smart addressing or HIFAS) and a standard drive method (called a voltage averaging method), both of which are well known among those skilled in the art to which the invention pertains.
Another method, called the alternate current (AC) drive method, is also employable which includes the step of inverting periodically, i.e. once per specified period, respective drive voltages applied to said plurality of segment electrodes and said plurality of common electrodes.
In the Alt Pleshko drive method, when an alternate current signal (M) is at High (simply referred to as xe2x80x9cHxe2x80x9d hereinafter) level, a drive voltage of Vsh is applied to each segment electrode of data xe2x80x9c1xe2x80x9d while letting a drive voltage of Vsl be applied to each segment electrode of data xe2x80x9c0xe2x80x9d as an example shown in FIG. 7.
In addition, a drive voltage of Vcl is applied to a selected common electrode while simultaneously a drive voltage of Vm is applied to non-select common electrodes.
Note here that the drive voltage of Vm is applied to such non-select common electrodes irrespective of whether the alternate current signal (M) is at H level or Low (xe2x80x9cLxe2x80x9d) level.
Furthermore, when the alternate current signal (M) is at L level, the drive voltage of Vsl is applied to each segment electrode of data xe2x80x9c1xe2x80x9d while the drive voltage of Vsh is applied to each segment electrode of data xe2x80x9c0xe2x80x9d as an example shown in FIG. 7.
Additionally a drive voltage of Vch is applied to a common electrode presently selected.
Note that FIG. 7 shows some major voltage waveforms in the case of performing white displaying, wherein these drive voltages are to be supplied by a power supply circuitry. =p An equivalent circuitry of the STN liquid crystal display panel may be represented by a circuit shown in FIG. 6, which is considered as a circuit with liquid crystal capacitors (CLC) being formed at intersections between the segment electrodes 10 and the common electrodes 11.
However, in the event that both the segment electrodes 10 and common electrodes 11 change or vary in potential level of the voltages being applied thereto, waveform rounding deformation or distortion will always occur in such applied voltages with no exceptions due to a relation of electrical interconnect lead resistivities of the segment electrodes 10 and common electrodes 11 versus the liquid crystal capacitors (CLC), as in a voltage waveform that is applied to a segment electrode 10 shown in FIG. 8 as an example.
Such waveform distortion would result in a decrease in effective value of a voltage as applied to each pixel upon changing of its potential level-for example, in liquid crystal display panels of the normally-off type, the effective voltage reduction leads to an appreciable decrease in brightness of those images being visually displayed at corresponding locations on a panel screen.
The description of the phenomenon stated above will be collectively referred to as the xe2x80x9cshadowingxe2x80x9d hereafter.
Once this shadowing takes place at specific lines on the screen of a liquid crystal display panel, the resultant display image contains black fine stripe-shaped noises viewable like hair-lines to human eyes, which results in a significant decrease in quality of images displayed on the screen of such liquid crystal display panel.
Prior known remedies for such a problem include a method shown in FIGS. 9 to 11 or another method shown in FIGS. 12-14.
The shadowing correction/compensation method shown in FIGS. 9-11 is that, as shown in FIG. 10, a time point at which a drive voltage being applied to a segment electrode(s) 10 while changes in potential level are detected by an exclusive logical sum circuit (EXOR) to which a presently incoming data and its preceding data are inputted. Then an AND circuit (AND1) is used to obtain a logical product between an output of the exclusive logical sum circuit (EXOR) and a correction pulse thereby causing a correction-for-compensation signal to stay at H level within a time period in which the correction pulse is at H level.
As shown in FIG. 9, when this correction signal stays at H level, an output of an AND circuit (AND1) is set at L level while an output of a NAND circuit (NAND1) is forced to be at H level, which thereby causes both an N type MOS transistor (simply referred to as xe2x80x9cNMOSxe2x80x9d hereinafter) (NM1) and a P type MOS transistor (simply referred to as xe2x80x9cPMOSxe2x80x9d hereafter) (PM1) to turn off.
Alternatively, when the correction signal is at H level, either a PMOS (PM2) or NMOS (NM2) are turned on the basis of this correction signal and the present data value.
Whereby, when the correction signal is at H level, a drive voltage of either Vshh or Vsll is applied to the segment electrode.
In short, this method applies a pulse-like correction voltage (e.g. pulses 15 of FIG. 11) when the drive voltage being applied to a segment electrode 10 changes in potential level in order to ensure that an effective voltage applied to a pixel when the drive voltage applied to the segment electrode 10 becomes identical to an effective voltage applied to the pixel so that the drive voltage as applied to segment electrode 10 does not change in potential level as shown in FIG. 11.
It should be noted in FIG. 9 that a DISPOFF signal is set to control on and off of the liquid crystal display panel, wherein the liquid crystal display panel is driven to display images on its screen when the DISPOFF signal stays at H level, and no images are displayed on the liquid crystal display panel when the DISPOFF signal is at L level.
More specifically, when this DISPOFF signal is at L level, the PMOS (PM1) and NMOS (NM1) turn off whereas PMOS (PM3) and NMOS (NM3) turn on, which causes a non-select voltage (Vm) to be applied to segment electrodes.
Another prior art shadowing correction/compensation method is shown in FIGS. 12-14. As shown in FIG. 13, a time point at which a drive voltage being applied to a segment electrode 10 is kept unchanged in potential level which is detected by a coincidence circuit (AGR) with the presently incoming data and its preceding data being input thereto; then, an AND circuit (AND1) is used to gain a logical product between an output of the coincidence circuit (AGR) and a correction pulse thereby a correction-for-compensation signal is caused to stay at H level when the correction pulse is at H level.
As shown in FIG. 12, when this correction signal stays at H level, an output of AND circuit (AND2) is at L level while an output of NAND circuit (NAND1) is forced to be at H level, which causes NMOS (NM1) and PMOS (PM1) to turn off. Alternatively, when the correction signal is at H level, PMOS (PM3) and NMOS (NM3) turn on.
Whereby, when the correction signal is at H level, the non-select voltage (Vm) is applied to segment electrodes.
In short, as shown in FIG. 14, this method applies the non-select voltage (Vm) (e.g. pulses 16 of FIG. 14) to more than one segment electrode when the drive voltage applied to such segment electrode remains unchanged in potential level, thereby reducing any voltage as applied to pixels when the drive voltage being applied to the segment electrode is kept unchanged in potential level in order to guarantee that when an effective voltage applied to pixels the drive voltage applied to the segment electrode does not change in potential level, which is identical to an effective voltage being applied to the pixel while the drive voltage as applied to the segment electrode has actually changed in potential level.
However, while the shadowing correction method shown in FIGS. 9-11 offers successful shadowing correctability, this advantage does come with a price of two separate transistors, e.g. PMOS (PM2) and NMOS (NM2), as output stage transistors in applying drive voltages of (Vshh, Vsll) to the segment electrodes 10.
The need to employ these PMOS (PM2) and NMOS (NM2) would disadvantageously result in an increase in chip area to accommodate large currents, which in turn leads to an increase in segment driver areas thus increasing production costs.
The shadowing correction method shown in FIGS. 12-14 although does not take the PMOS (PM2) and NMOS (NM2) as in the method shown in FIGS. 9-11, it needs a potential change in output voltages which results in an increase in frequency components of voltages so as to decrease the efficiency of the shadowing correction/compensation.
The present invention has been made in order to avoid the problems faced with the prior art, and a primary objective of the invention is to provide a technique adaptable for use in liquid crystal display devices to prevent degradation of display images otherwise occurring due to waveform rounding deformation or distortion of drive voltages as applied to data lines without having to increase the area of a semiconductor chip or chips in data line driver means.
To attain the object, the invention provides a liquid crystal display device which includes a plurality of scan electrodes, display elements that oppose the plurality of scan electrodes with a layer of liquid crystal disposed therebetween and have a plurality of data electrodes crossing or intersecting at right angles with the plurality of scan electrodes, data electrode driver means for applying to the plurality of data electrodes any voltage corresponding to the display data and the non-select voltage as well as a correction-for-compensation voltage with a potential difference relative to the non-select voltage being greater than a potential difference between the voltage corresponding to the display data and the non-select voltage, a power supply circuit for supplying the data electrode driver means with the above-noted voltage corresponding to the display data and the non-select voltage plus the compensation voltage, and a compensation pulse generator circuit for generation of more than one compensation pulse, wherein the data driver means includes voltage selector means for selecting the compensation voltage when the non-select voltage and compensation voltage are inputted thereto with the display elements being rendered operative or turned on and for selecting the non-select voltage within a time period in which the display elements are turned off, and voltage application means, for applying the compensation voltage as output from the voltage selector means to a specified data electrode(s) whereat the display data has changed from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d or alternatively from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d within the period in which the display elements are turned on and also within a time period in which input is made from the compensation pulse generator circuit and for applying the non-select voltage being output from the voltage selector means within a time period in which the display elements are turned off.
Another principal feature of the instant invention is that the voltage selector means is operable to select either the compensation voltage or the non-select voltage on the basis of a control signal to control on and off of the display elements.
A further feature of the invention is that the device further includes a logical product circuit as provided in a respective one of the data electrodes for determination through digital computation of a logical product of a presently generated display data and the inverted value of its preceding display data as well as the compensation pulse as input from the compensation pulse generator means and for outputting a compensation signal, and that the voltage application means is operable to apply either one of the compensation voltage and the non-select voltage to each data electrode on the basis of the compensation signal as output from the logical product circuit and also a control signal to control on and off of the display elements.